New arithmetic coder/decoder architectures based on pipelining

Proceedings of the International Conference on Application-Specific Systems, Architectures and Processors

Volumn , Issue , 1997, Pages 106-115

  Osorio, Roberto ^a   Bruguera, Javier D ^a  

^a UNIVERSITY OF SANTIAGO DE COMPOSTELA   (Spain)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COST EFFECTIVENESS; DIGITAL ARITHMETIC; PIPELINE PROCESSING SYSTEMS; RECURSIVE FUNCTIONS; STORAGE ALLOCATION (COMPUTER); VLSI CIRCUITS;

ARITHMETIC ENCODING/DECODING; MULTILEVEL IMAGES;

IMAGE CODING;

EID: 0030721947     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (9)