5 to 130 V level shifter composed of thin gate oxide dual terminal drain PMOSFETs

IEEE International Symposium on Power Semiconductor Devices & ICs (ISPSD)

Volumn , Issue , 1997, Pages 345-348

  Mori, Kazuhisa ^a   Tanaka, Koji ^a   Kobayashi, Kenya ^a   Takahashi, Kenichiro ^a   Takahashi, Mitsuasa ^a  

^a NEC CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; COST EFFECTIVENESS; GATES (TRANSISTOR); INTEGRATED CIRCUIT LAYOUT; PLASMA DISPLAY DEVICES;

LEVEL SHIFTERS;

MOSFET DEVICES;

EID: 0030721266     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (1)