Complete x86 instruction trace generation from hardware bus collect

Conference Proceedings of the EUROMICRO

Volumn , Issue , 1997, Pages 402-408

  Bosch, P ^a   Carloganu, A ^a   Etiemble, D ^a  

^a CNRS   (France)

Author keywords

[No Author keywords available]

Indexed keywords

ARCHITECTURAL IMPROVEMENTS; EXECUTION TRACE; HARDWARE/SOFTWARE; MEMORY HIERARCHY; PERFORMANCE DATA; TRACE DRIVEN SIMULATION; TRACE GENERATION;

BENCHMARKING; HARDWARE; COMPUTER HARDWARE; COMPUTER SOFTWARE; LOGIC GATES; MICROPROCESSOR CHIPS;

INFORMATION TECHNOLOGY; REDUCED INSTRUCTION SET COMPUTING;

LOGIC ANALYZERS; TRACE GENERATION;

EID: 0030719237     PISSN: 10896503     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/EURMIC.1997.617339     Document Type: Conference Paper

References (7)

1. D. Anderson and T. Shanley. Pentium Processor System Architecture. MindShare, Inc., 1995.
2. K. Flanagan, K. Grimsrud, J. Archibald, and B. Nelson. BACH: BYU Adrress Collection Hardware. Technical report, Department of Electrical and Computer Engineering, Brighan Young University, 1992.
3. G. Warn. Spa package, 1991.
4. J. K. Flanagan and B.E. Nelson and J.K. Archibald and K. Grimsrud. BYU Address Collection Hardware, The Collection of Complete Traces. Proceedings of the Sixth International Conference on Modelling Techniques and Tools for Computer Performance Evaluation, 1992.
5. J. Pierce and T. Mudge. IDTrace-A Tracing Tool for i486 Simulation. Technical report, Department of Electrical Engineering and Computer Science, The University of Michigan, 1992.
6. A. Poursepanj. The powerpc, performance modeling methodology. In ACM, editor, Communications of the ACM, volume 37, pages 47-55. June 1994.
7. M. Smith. Tracing with pixie. Technical report, Center for Integrated Systems, 1991.