Area-time performance of VLSI FIR filter architectures based on residue arithmetic

Conference Proceedings of the EUROMICRO

Volumn , Issue , 1997, Pages 576-583

  Paliouras, V ^a   Stouraitis, T ^a  

^a UNIVERSITY OF PATRAS   (Greece)

Author keywords

[No Author keywords available]

Indexed keywords

BINARY STRUCTURES; CHINESE REMAINDER THEOREM; FILTER ARCHITECTURE; OPTIMIZATION PROCEDURES; PERFORMANCE MODEL; RESIDUE ARITHMETIC; RESIDUE NUMBER SYSTEM;

FIR FILTERS; NUMBERING SYSTEMS; OPTIMIZATION; COMPUTATIONAL COMPLEXITY; DIGITAL ARITHMETIC; VLSI CIRCUITS;

INFORMATION TECHNOLOGY; DIGITAL FILTERS;

CHINESE REMAINDER THEOREM (CRT) ARCHITECTURES; MULTIPLY BY CONSTANT UNITS (MCU); RESIDUE NUMBER SYSTEM (RNS);

EID: 0030718683     PISSN: 10896503     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/EURMIC.1997.617376     Document Type: Conference Paper

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