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Volumn , Issue , 1997, Pages 172-181

Interactive codesign for real-time embedded control systems: Task graph generation from SA/VHDL models

Author keywords

[No Author keywords available]

Indexed keywords

BEHAVIORAL ANALYSIS; CO-DESIGN APPROACH; EMBEDDED CONTROL SYSTEMS; FUNCTIONAL BEHAVIORS; FUNCTIONAL SPECIFICATION; HIERARCHICAL DECOMPOSITIONS; HW/SW PARTITIONING; INFORMATION CONCERNING;

EID: 0030711367     PISSN: 10896503     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/EURMIC.1997.617255     Document Type: Conference Paper
Times cited : (8)

References (13)
  • 2
    • 0029735299 scopus 로고    scopus 로고
    • Design of an optimal loosely coupled heterogeneous multiprocessor system
    • Paris, France
    • A. Bender. Design of an optimal loosely coupled heterogeneous multiprocessor system. In Proceedings of The European Design &Test Conference, pages 275-281, Paris, France, 1996.
    • (1996) Proceedings of the European Design &Test Conference , pp. 275-281
    • Bender, A.1
  • 4
    • 0028483811 scopus 로고
    • Computer-aided hardware-software code-sign
    • August
    • G. DeMicheli. Computer-aided hardware-software code-sign. IEEE Micro, pages 10-16, August 1994.
    • (1994) IEEE Micro , pp. 10-16
    • Demicheli, G.1
  • 5
    • 84943730764 scopus 로고
    • Hardware/software co-synthesis for microcontrollers
    • December
    • R. Ernst, J. Henkel, and T. Benner. Hardware/software co-synthesis for microcontrollers. IEEE Design &Test Magazine, 10(4):64-75, December 1993.
    • (1993) IEEE Design &Test Magazine , vol.10 , Issue.4 , pp. 64-75
    • Ernst, R.1    Henkel, J.2    Benner, T.3
  • 8
    • 14744280789 scopus 로고
    • Functional specification and verification of digital system by using vhdl combined with graphical structured analysis
    • Stockholm, Sweden
    • M. Kauppi and J.-P. Soininen. Functional specification and verification of digital system by using vhdl combined with graphical structured analysis. In Proceedings of the 2nd European Conference on VHDL Methods, Stockholm, Sweden, 1991.
    • (1991) Proceedings of the 2nd European Conference on VHDL Methods
    • Kauppi, M.1    Soininen, J.-P.2
  • 10
    • 14744269404 scopus 로고    scopus 로고
    • A formal validation environment for functional specifications
    • Toledo, Spain
    • J.-P. Soininen, J. Saarikettu, V. Veijalainen, and T. Huttunen. A formal validation environment for functional specifications. In CHDL97, Toledo, Spain, 1997.
    • (1997) CHDL97
    • Soininen, J.-P.1    Saarikettu, J.2    Veijalainen, V.3    Huttunen, T.4


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.