Suppression of bit-line-induced disturbance in SOI DRAM/SRAM cells by bipolar embedded source structure (BESS)

Digest of Technical Papers - Symposium on VLSI Technology

Volumn , Issue , 1997, Pages 157-158

  Horiuchi, Masatada ^a   Sakata, Takeshi ^a   Kimura, Shin'ichiro ^a  

^a HITACHI LTD   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

ANNEALING; BIPOLAR TRANSISTORS; CELLULAR ARRAYS; ELECTRIC BREAKDOWN OF SOLIDS; ELECTRIC RESISTANCE; ION IMPLANTATION; LEAKAGE CURRENTS; MOSFET DEVICES; SEMICONDUCTING SILICON; SEMICONDUCTOR DEVICE MANUFACTURE; SEMICONDUCTOR DEVICE TESTING; SILICON ON INSULATOR TECHNOLOGY;

DYNAMIC RANDOM ACCESS MEMORY (DRAM); FLOATING BODY EFFECTS; STATIC RANDOM ACCESS MEMORY (SRAM);

RANDOM ACCESS STORAGE;

EID: 0030708106     PISSN: 07431562     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/vlsit.1997.623746     Document Type: Conference Paper

References (0)