Memory efficient array architecture for real-time motion estimation

Proceedings of the International Parallel Processing Symposium, IPPS

Volumn , Issue , 1997, Pages 28-32

  Moshnyaga, Vasily G ^a   Tamaru, Keikichi ^a  

^a KYOTO UNIVERSITY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

BANDWIDTH COMPRESSION; COMPUTATIONAL METHODS; COMPUTER ARCHITECTURE; HIGH DEFINITION TELEVISION; IMAGE CODING; IMAGE COMPRESSION; REAL TIME SYSTEMS; STORAGE ALLOCATION (COMPUTER); VLSI CIRCUITS;

REAL TIME VIDEO PICTURE MOTION ESTIMATION; VIDEO MEMORY DISTRIBUTION; VIDEO MEMORY SHARING;

PARALLEL PROCESSING SYSTEMS;

EID: 0030706567     PISSN: 10637133     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (9)