Implementation of a digital signal processor in a DBF self-beam-steering array antenna

IEICE Transactions on Communications

Volumn E80-B, Issue 1, 1997, Pages 166-175

  Tanaka, Toyohisa ^a,b   Miura, Ryu ^a,c   Karasawa, Yoshio ^a  

^a ADVANCED TELECOMMUNICATIONS RESEARCH INSTITUTE INTERNATIONAL   (Japan)

^b Hewlett Packard Japan Ltd   (Japan)

^c Communications Research Laboratory ^*  (Japan)

Author keywords

Dbf antenna; DSP; FPGA ASIC; Maximal ratio combining; Self beam steering; Self phasing

Indexed keywords

ANECHOIC CHAMBERS; APPLICATION SPECIFIC INTEGRATED CIRCUITS; DIGITAL SIGNAL PROCESSING; GATES (TRANSISTOR); MOBILE TELECOMMUNICATION SYSTEMS;

DIGITAL BEAMFORMING (DBF) SELF BEAM STEERING ARRAY ANTENNA; FIELD PROGRAMMABLE GATE ARRAY (FPGA);

ANTENNA PHASED ARRAYS;

EID: 0030703945     PISSN: 09168516     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Article

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