Low-noise 1.6-GHz CMOS PLL with on-chip loop filter

Proceedings of the Custom Integrated Circuits Conference

Volumn , Issue , 1997, Pages 407-410

  Parker, James ^a   Ray, Daniel ^a  

^a Level One Communications   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; FREQUENCY DIVIDING CIRCUITS; PASSIVE FILTERS; SPURIOUS SIGNAL NOISE; VARIABLE FREQUENCY OSCILLATORS;

ON CHIP LOOP FILTERS; PHASE DETECTORS;

PHASE LOCKED LOOPS;

EID: 0030689957     PISSN: 08865930     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (8)