New approach for the extraction of gate voltage dependent series resistance and channel length reduction in CMOS transistors

IEEE International Conference on Microelectronic Test Structures

Volumn , Issue , 1997, Pages 188-193

  Brut, H ^a   Juge, A ^a   Ghibaudo, G ^a  

^a STMICROELECTRONICS   (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; ELECTRIC RESISTANCE; INTEGRATED CIRCUIT LAYOUT; INTEGRATED CIRCUIT TESTING; VOLTAGE MEASUREMENT;

RESISTANCE BASED EXTRACTION METHOD;

GATES (TRANSISTOR);

EID: 0030683782     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (16)