Performance-driven placement algorithm with simultaneous place & route optimization for analog IC's

Proceedings of European Design and Test Conference

Volumn , Issue , 1997, Pages 389-394

  Prieto, Juan A ^a   Rueda, Adoracion ^a   Quintana, Jose M ^a   Huertas, Jose L ^a  

^a INSTITUTO DE MICROELECTRÓNICA DE SEVILLA   (Spain)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; CELLULAR ARRAYS; COMPUTATIONAL COMPLEXITY; HEURISTIC METHODS; OPTIMIZATION; TREES (MATHEMATICS);

PERFORMANCE DRIVEN PLACEMENT ALGORITHM;

INTEGRATED CIRCUIT LAYOUT;

EID: 0030679976     PISSN: 10661409     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (10)