Pseudo-hierarchical methodology for high performance microprocessor design

Proceedings of the International Symposium on Physical Design

Volumn , Issue , 1997, Pages 124-129

  Bertolet, A ^a   Carpenter, K ^a   Carrig, K ^a   Chu, A ^a   Dean, A ^a   Ferraiolo, F ^a   Kenyon, S ^a   Phan, D ^a   Petrovick, J ^a   Rodgers, G ^a   Willmott, D ^a   Bairley, T ^a   Decker, T ^a   Girardi, V ^a   Lapid, Y ^a   et al , ^a  

^a IBM   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; CMOS INTEGRATED CIRCUITS; DATABASE SYSTEMS; INTEGRATED CIRCUIT LAYOUT;

CLOCK NETWORK INSERTION; POWER GRID GENERATION; TIMING DRIVEN PLACEMENT;

MICROPROCESSOR CHIPS;

EID: 0030679122     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (7)