Integrating on-chip temperature sensors into DfT schemes and BIST architectures

Proceedings of the IEEE VLSI Test Symposium

Volumn , Issue , 1997, Pages 440-445

  Szekely, V ^a   Rencz, M ^a   Courtois, B ^a  

^a BUDAPEST UNIVERSITY OF TECHNOLOGY AND ECONOMICS   (Hungary)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; ELECTRONICS PACKAGING; INTEGRATED CIRCUIT LAYOUT; SENSORS; THERMODYNAMIC STABILITY;

DESIGN FOR THERMAL TESTABILITY (DFTT); ONCHIP TEMPERATURE SENSORS;

INTEGRATED CIRCUIT TESTING;

EID: 0030677575     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (10)