On-line testable UART implemented using IFIS

Proceedings of the IEEE VLSI Test Symposium

Volumn , Issue , 1997, Pages 344-349

  Yeandel, J ^a   Thulborn, D ^a   Jones, S ^a  

^a LOUGHBOROUGH UNIVERSITY   (United Kingdom)

Author keywords

[No Author keywords available]

Indexed keywords

ERROR DETECTION; INTEGRATED CIRCUIT TESTING; LOGIC CIRCUITS; ONLINE SYSTEMS;

FIELD PROGRAMMABLE GATE ARRAY (FPGA); IF IT FAILS IT STOPS (IFIS); ONLINE TESTING; UNIVERSAL ASYNCHRONOUS RECEIVER TRANSMITTER (UART);

COMPUTER AIDED LOGIC DESIGN;

EID: 0030672594     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (10)