Synthesis preprocessor that converts implicit style Verilog into one-hot designs

Proceedings - IEEE International Verilog HDL Conference

Volumn , Issue , 1997, Pages 38-45

  Arnold, Mark G ^a   Shuler, James D ^a  

^a UNIVERSITY OF WYOMING   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTATIONAL LINGUISTICS; COMPUTER HARDWARE DESCRIPTION LANGUAGES; COMPUTER SIMULATION; COMPUTER SOFTWARE; ELECTRIC NETWORK SYNTHESIS; PROGRAM PROCESSORS;

SOFTWARE PACKAGE SYNOPSYS DESIGN COMPILER; VERILOG HARDWARE DESCRIPTION LANGUAGE;

COMPUTER AIDED LOGIC DESIGN;

EID: 0030671829     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (11)