Exploring module selection space for architectural synthesis of low power designs

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn 3, Issue , 1997, Pages 1532-1535

  Shen, Z X ^a   Jong, C C ^a  

^a NANYANG TECHNOLOGICAL UNIVERSITY   (Singapore)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC NETWORK SYNTHESIS; ELECTRIC NETWORK TOPOLOGY; OPTIMIZATION;

BRANCH AND BOUND APPROACH;

LOGIC DESIGN;

EID: 0030656031     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)