Robust 0.15 μm CMOS technology with CoSi2 salicide and shallow trench isolation

Digest of Technical Papers - Symposium on VLSI Technology

Volumn , Issue , 1997, Pages 125-126

  Kawaguchi, H ^a   Abiko, H ^a   Inoue, K ^a   Saito, Y ^a   Yamamoto, T ^a   Hayashi, Y ^a   Masuoka, S ^a   Ono, A ^a   Tamura, T ^a   Tokunaga, K ^a   Yamada, Y ^a   Yoshida, K ^a   Sakai, I ^a  

^a NEC CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

ANNEALING; CMOS INTEGRATED CIRCUITS; COBALT COMPOUNDS; SPUTTERING;

SALICIDE; SHALLOW TRENCH ISOLATION (STI);

SEMICONDUCTOR DEVICE MANUFACTURE;

EID: 0030654848     PISSN: 07431562     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (6)