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Volumn , Issue , 1997, Pages 29-31
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Layout optimization of ESD protection TFO-NMOS by two-dimensional device simulation
a a a a |
Author keywords
[No Author keywords available]
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Indexed keywords
COMPUTER SIMULATION;
INTEGRATED CIRCUIT LAYOUT;
ION IMPLANTATION;
OPTIMIZATION;
SEMICONDUCTOR DEVICE STRUCTURES;
SEMICONDUCTOR JUNCTIONS;
CURRENT TO FAILURE PROFILES;
HEAT TRANSFER EQUATION;
TIME TO FAILURE PROFILES;
TWO DIMENSIONAL DEVICE SIMULATION;
MOS DEVICES;
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EID: 0030654833
PISSN: None
EISSN: None
Source Type: Conference Proceeding
DOI: None Document Type: Conference Paper |
Times cited : (1)
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References (4)
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