Efficient VLSI implementation of a 3-layer threshold network

IEEE International Conference on Neural Networks - Conference Proceedings

Volumn 2, Issue , 1997, Pages 888-893

  Kim, J H ^a   Park, Sung Kwon ^b   Han, Youngnam ^c   Oh, Hyunseo ^c   Han, M S ^d  

^a UNIVERSITY OF LOUISIANA AT LAFAYETTE   (United States)

^b Hanyang University   (South Korea)

^c Electronics and Telecommunications Research Institute (ETRI)   (South Korea)

^d SERI   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

ARBITRARY SWITCHING; CMOS VLSI TECHNOLOGY; GUARANTEED CONVERGENCE; HIDDEN LAYERS; INTEGER WEIGHTS; PARITY FUNCTIONS; THRESHOLD NETWORKS; VLSI IMPLEMENTATION;

NEURAL NETWORKS; SWITCHING FUNCTIONS; THRESHOLD ELEMENTS; CMOS INTEGRATED CIRCUITS; CONVERGENCE OF NUMERICAL METHODS; ELECTRIC NETWORK SYNTHESIS; GATES (TRANSISTOR); LEARNING ALGORITHMS; VECTORS; VLSI CIRCUITS;

NETWORK LAYERS; NEURAL NETWORKS;

EXPAND AND TRUNCATE LEARNING (ETL); THREE LAYER THRESHOLD NETWORK (TLTN);

EID: 0030653260     PISSN: 10987576     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICNN.1997.616142     Document Type: Conference Paper

References (5)

1. Caudill, M. and C. Butler, "Naturally Intelligent systems", The MIT Press, 1990.
2. Chung, H. S. et. al., "A Novel Digital Multiplier Chip Based on the Neural Network", ISCAS, LA, May 1990.
3. Kim, J. H. and S. K. Park, "The Geometrical Learning of Biological Neural Networks", IEEE Trans, on Neural Networks, Jan. 1995.
4. Minsky, M. and S. Papert, "An Introduction to Computational Geometry", The MIT Press, 1969
5. Muroga, S., "Threshold Logic and Its Applications", John Wiley & Sons, Inc. 1971.