Throughput, delay and packet loss analyzes of input buffered ATM switch architectures

Systems Analysis Modelling Simulation

Volumn 28, Issue 1-4, 1997, Pages 69-75

  Macii, Alberto ^a   Macii, Enrico ^a   Wolf, Tara ^a  

^a POLITECNICO DI TORINO   (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

BUFFER STORAGE; COMMUNICATION CHANNELS (INFORMATION THEORY); COMPUTER ARCHITECTURE; DELAY CIRCUITS; ELECTRIC NETWORK ANALYSIS; PACKET SWITCHING; PROBABILITY; STORAGE ALLOCATION (COMPUTER);

MULTICAST ARCHITECTURES;

ASYNCHRONOUS TRANSFER MODE;

EID: 0030652999     PISSN: 02329298     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Article

References (3)