Use of statecharts-related description to achieve testable design of control subsystems

Proceedings of the IEEE Great Lakes Symposium on VLSI

Volumn , Issue , 1997, Pages 118-123

  Fummi, F ^a   Sami, M G ^a   Tartarini, F ^a  

^a POLITECNICO DI MILANO   (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

AUTOMATIC TESTING; COMPUTER HARDWARE DESCRIPTION LANGUAGES; CONTROL SYSTEMS; FAILURE ANALYSIS; FINITE AUTOMATA; REDUNDANCY;

CONTROL SUBSYSTEMS; FAULT COVERAGE; FUNCTIONALLY REDUNDANT FAULTS; REDUNDANCY REMOVAL; STATECHARTS DESCRIPTION; TEST PATTERN GENERATION; TESTABLE DESIGN;

SEQUENTIAL CIRCUITS;

EID: 0030651651     PISSN: 10661395     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (12)