Quick placement with geometric constraints

Proceedings of the Custom Integrated Circuits Conference

Volumn , Issue , 1997, Pages 561-564

  Malavasi, Enrico ^a   Ganley, Joseph L ^a   Charbon, Edoardo ^a  

^a CADENCE DESIGN SYSTEMS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; CONSTRAINT THEORY; INTEGRATED CIRCUIT LAYOUT; LOGIC CIRCUITS; MICROPROCESSOR CHIPS; SIMULATED ANNEALING;

DEVICE LEVEL PLACER (DLP);

LOGIC DEVICES;

EID: 0030650148     PISSN: 08865930     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (11)