High performance memory and bus architecture for implementing 2D FFT on a SPMD machine

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn 3, Issue , 1997, Pages 2032-2035

  Cavadini, M ^a   Wosnitza, M ^a   Thaler, M ^a   Troster, G ^a  

^a ETH ZURICH   (Switzerland)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; BANDWIDTH; DATA COMMUNICATION SYSTEMS; FAST FOURIER TRANSFORMS; RANDOM ACCESS STORAGE;

DYNAMIC RANDOM ACCESS MEMORY (DRAM); SINGLE PROGRAM MULTIPLE DATA (SMPD) ARCHITECTURE;

COMPUTER ARCHITECTURE;

EID: 0030648298     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (11)