Dual basis systolic multipliers for GF(2m)

IEE Proceedings: Computers and Digital Techniques

Volumn 144, Issue 1, 1997, Pages 43-46

  Fenn, S T J ^a   Benaissa, M ^a   Taylor, D ^a  

^a UNIVERSITY OF HUDDERSFIELD   (United Kingdom)

Author keywords

Error correcting codes; Finite field multipliers; RS codes

Indexed keywords

ALGORITHMS; CODES (SYMBOLS); ERROR CORRECTION; INTEGRATED CIRCUIT LAYOUT; PERFORMANCE; PIPELINE PROCESSING SYSTEMS; VLSI CIRCUITS;

DUAL BASIS SYSTOLIC MULTIPLIERS; ERROR CORRECTING CODES; FINITE FIELD MULTIPLIERS; REED-SOLOMON CODES;

MULTIPLYING CIRCUITS;

EID: 0030648046     PISSN: 13502387     EISSN: None     Source Type: Journal    
DOI: 10.1049/ip-cdt:19970660     Document Type: Article

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