Architectural exploration using verilog-based power estimation: a case study of the IDCT

Proceedings - Design Automation Conference

Volumn , Issue , 1997, Pages 415-420

  Xanthopoulos, Thucydides ^a   Yaoi, Yoshifumi ^a   Chandrakasan, Anantha ^a  

^a MASSACHUSETTS INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; CAPACITANCE; FLIP FLOP CIRCUITS; IMAGE CODING; LOGIC GATES; SIMULATION; TRANSISTORS;

DISTRIBUTED ARITHMETIC; INVERSE DISCRETE COSINE TRANSFORM; VERILOG BASED POWER ESTIMATION;

DIGITAL CIRCUITS;

EID: 0030646145     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)