On the use of reset to increase the testability of interconnected finite-state machines

Proceedings of European Design and Test Conference

Volumn , Issue , 1997, Pages 554-559

  Pomeranz, Irith ^a   Reddy, Sudhakar M ^a  

^a UNIVERSITY OF IOWA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC NETWORK ANALYSIS; FORMAL LOGIC; FOURIER TRANSFORMS;

INTERCONNECTED FINITE STATE MACHINES; RESET MECHANISMS;

SEQUENTIAL CIRCUITS;

EID: 0030646136     PISSN: 10661409     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (14)