Par-POPINS: A timing-driven parallel placement method with the Elmore delay model for row based VLSIs

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Volumn , Issue , 1997, Pages 133-140

  Koide, Tetsushi ^a   Ono, Mitsuhiro ^a   Wakabayashi, Shin'ichi ^a   Nishimaru, Yutaka ^a  

^a HIROSHIMA UNIVERSITY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

INTEGRATED CIRCUIT LAYOUT; ITERATIVE METHODS; MICROPROCESSOR CHIPS; NONLINEAR PROGRAMMING; PARALLEL ALGORITHMS; STORAGE ALLOCATION (COMPUTER);

ELMORE DELAY MODEL; PARALLEL PLACEMENT METHOD; SOFTWARE PACKAGE POPINS;

VLSI CIRCUITS;

EID: 0030644888     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (22)