Burn-in economics model for multi-chip modules

Electronics Letters

Volumn 32, Issue 25, 1996, Pages 2349-2351

  Alani, A ^a   Dislis, C ^b   Jalowiecki, I ^c  

^a LSI Logic Europe   (United Kingdom)

^b UNIVERSITY OF READING   (United Kingdom)

^c BRUNEL UNIVERSITY   (United Kingdom)

Author keywords

Multichip models; Reliability

Indexed keywords

COST EFFECTIVENESS; ECONOMICS; RELIABILITY; SEMICONDUCTOR DEVICE MANUFACTURE; SEMICONDUCTOR DEVICE MODELS;

BURN IN ECONOMICS MODEL;

MULTICHIP MODULES;

EID: 0030571411     PISSN: 00135194     EISSN: None     Source Type: Journal    
DOI: 10.1049/el:19961559     Document Type: Article

References (3)

1. ARSENAULT, J.RE., and ROBERTS, J.A.: 'Reliability and maintainability of electronic systems' (Pitman Publishing Ltd., 1980)
2. JENSENN, F., and PETERSEN, N.E.: 'Burn-in: An engineering approach to the design and analysis of burn-in procedures' (John Wiley, 1982)
3. DISLIS, C., AL-ANI, A.F., and JALOWIECKI, I.P.: 'MCM quality and cost analysis using economics model'. Int. Test Conf., Washington, USA, October 1995, pp. 430-437