A layout design system for complex made-to-order products

Journal of Engineering Design

Volumn 7, Issue 4, 1996, Pages 363-375

  Smith, N ^a   Hills, W ^a   Cleland, G ^a  

^a NEWCASTLE UNIVERSITY   (United Kingdom)

Author keywords

[No Author keywords available]

Indexed keywords

EID: 0030444741     PISSN: 09544828     EISSN: None     Source Type: Journal    
DOI: 10.1080/09544829608907946     Document Type: Article

References (13)

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9. HILLS, W. & BARLOW, M. (1994) The application of simulated annealing within a knowledge based layout design system, Adaptive Computing in Engineering Design and Contol Conference, Plymouth, UK.
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11. LEE, C.Y. (1961) An algorithm for path connections and its applications, IRE Transactions on Electronic Computers, September, p. 346.
12. WITTE, E.E. (1991) Parallel simulated annealing using speculative computation, Transactions on Parallel and Distributed Systems, 2, pp. 483-493.
13. JAYARAMAN, R. et al. (1988) Error tolerance in parallel simulated annealing techniques, Computer Design VLSI in Computers and Design: International Conference, pp. 545-548.