Mixing fixed and reconfigurable logic for array processing

IEEE Symposium on FPGAs for Custom Computing Machines, Proceedings

Volumn , Issue , 1996, Pages 118-125

  Bakkes, P J ^a   du Plessis, J J ^a   Hutchings, B L ^a  

^a STELLENBOSCH UNIVERSITY   (South Africa)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMPUTER ARCHITECTURE; DIGITAL ARITHMETIC; LOGIC DESIGN; MATRIX ALGEBRA; VECTORS;

FIELD PROGRAMMABLE GATE ARRAYS (FPGA); RECONFIGURABLE LOGIC;

LOGIC GATES;

EID: 0030421943     PISSN: 10823409     EISSN: None     Source Type: None    
DOI: 10.1109/TAI.1996.560441     Document Type: Conference Paper

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