New High Voltage SOI Device Structure Eliminating Substrate Bias Effects

Technical Digest - International Electron Devices Meeting, IEDM

Volumn , Issue , 1996, Pages 477-480

  Nakagawa, Akio ^a   Yamaguchi, Yoshihiro ^a   Yasuhara, Norio ^a   Hirayama, Keizo ^a   Funaki, Hideyuki ^a  

^a TOSHIBA CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

BIAS VOLTAGE; SILICON COMPOUNDS; SUBSTRATES; BIPOLAR TRANSISTORS; CRYSTAL IMPURITIES; ELECTRIC BREAKDOWN; OXIDES; SEMICONDUCTING FILMS; SEMICONDUCTOR DEVICE MANUFACTURE; SEMICONDUCTOR DEVICE STRUCTURES; SEMICONDUCTOR DIODES; SILICON ON INSULATOR TECHNOLOGY;

CRYSTALLINE SILICONS; HIGH VOLTAGE SOI DEVICES; LATERAL IGBT; NEW HIGH; SEMI-INSULATING; SILICON LAYER; SUBSTRATE BIAS; SUBSTRATE BIAS EFFECTS; THICK BURIED OXIDES;

ELECTRIC BREAKDOWN; SEMICONDUCTOR DEVICES;

BURIED OXIDE; INSULATED GATE BIPOLAR TRANSISTORS; SEMI INSULATING POLYCRYSTALLINE SILICON LAYER; SILICON LAYER; SOI DEVICE STRUCTURE; SUBSTRATE BIAS EFFECTS;

EID: 0030421412     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IEDM.1996.553630     Document Type: Conference Paper

References (3)

1. [l]A.Nakagawa et al., 1992 IEEEIEDM Tech. Digest, p.229.
2. A.Nakagawa,Proc of ISPSD'91, p.16
3. Y.S.Huang et al., Proc. ofISPSD91, p.27.