Single-chip 4 × 500-MBd CMOS transceiver

IEEE Journal of Solid-State Circuits

Volumn 31, Issue 12, 1996, Pages 2004-2013

  Widmer, Albert X ^a,b,d,e,f   Wrenner, Kevin ^{b,f,g,h,i,j,k}   Ainspan, Herschel A ^b,l   Parker, Ben ^b,m,n,o   Austruy, Pierre ^c   Brezzo, Bernard ^c   Haen, Anne Marie ^c   Ewen, John F ^a,b   Soyuer, Mehmet ^b,p,q   Blanc, Alain ^c   Abbiate, Jean Claude ^c,r,s   Deutsch, Alina ^a,b   Shin, Hyun J ^b  

^a IEEE

^b IBM T J WATSON RESEARCH CENTER   (United States)

^c IBM   (France)

^d ETH ZURICH   (Switzerland)

^e Institute for Telecommunications ETH

^f IBM   (United States)

^g Department of Obstetrics Gynecology   (United States)

^h HEWLETT PACKARD COMPANY   (United States)

ⁱ Digit Communication IC Design Group

^j IBM Corporation ^*

^k Tau Beta Pi Association

^l Och Spine at New York Presbyterian Hospitals   (United States)

^m BOWDOIN COLLEGE   (United States)

ⁿ BROWN UNIVERSITY   (United States)

^o Mixed Sign Commun IC Design Group

^p MIDDLE EAST TECHNICAL UNIVERSITY   (Turkey)

^q UNIVERSITY OF CALIFORNIA   (United States)

^r UNIVERSITÉ DE LYON   (France)

^s Transport Network Nodes Department

more..

Author keywords

[No Author keywords available]

Indexed keywords

ASYNCHRONOUS TRANSFER MODE; INTERFACES (COMPUTER); MICROPROCESSOR CHIPS; PHASE LOCKED LOOPS; SIGNAL DISTORTION; SWITCHING SYSTEMS; TRANSCEIVERS;

ASYNCHRONOUS TRANSFER MODE SWITCH SYSTEM;

CMOS INTEGRATED CIRCUITS;

EID: 0030420392     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.545824     Document Type: Article

References (12)

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