Minimal delay test sets for unate gate networks

Proceedings of the Asian Test Symposium

Volumn , Issue , 1996, Pages 155-163

  Sparmann, U ^a   Mueller, H ^a   Reddy, S M ^a  

^a SAARLAND UNIVERSITY   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

DELAY TEST SETS; UNATE GATE NETWORKS (UGN);

CMOS INTEGRATED CIRCUITS; ELECTRIC DELAY LINES; ELECTRIC FAULT CURRENTS; ERROR DETECTION; INTEGRATED CIRCUIT LAYOUT; INTEGRATED CIRCUIT TESTING; LOGIC GATES;

LOGIC CIRCUITS;

EID: 0030419972     PISSN: 10817735     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (24)

1. Z. Barzilai and B.K. Rosen. Comparision of AC self-testing procedures. In International Test Conference, pages 89-91, 1983.
2. G.L. Smith. Model for delay faults based upon paths. In International Test Conference, pages 342-349, 1985.
3. W. Ke and P.R. Menon. Synthesis of delay-verifiable two-level circuits. In European Design and Test Conference, pages 297-301, 1994.
4. S.M. Reddy, C.J. Lin, and S. Patii. An automatic test pattern generator for the detection of path delay faults. In International Conference on CAD, pages 284-287, 1987.
5. K. Fuchs, F. Fink, and M.H. Schulz. DYNAMITE: an efficient automatic test pattern generation system for path delay faults. IEEE Transactions on CAD, pages 1323-1335,1991.
6. U. Sparmann, D. Luxenburger, K.T. Cheng, and S.M. Reddy. Fast identification of robust dependent path delay faults. In 32nd Design Automation Conference, pages 119-125, 1995.
7. W. Ke. Delay-Verification and Synthesis of Delay-Verifiable Circuits. PhD thesis, Department of ECE, University of Massachusetts Amherst, September 1994.
8. U. Sparmann, H. Müller, and S.M. Reddy. Universal delay test sets for logic networks. To appear in: IEEE Transactions on VLSI Systems, 1996. (Preliminary version available as technical report 5-30-94, Department of ECE, University of Iowa, Iowa City, May 1994).
9. R.H. Krambeck, CM. Lee, and H.-F.S. Law. Highspeed compact circuits with CMOS. IEEE Journal of Solid State Circuits, 1982.
10. N. Goncalves and H. DeMan. NORA: A racefree dynamic CMOS technique for pipelined logic structures. IEEE Journal of Solid State Circuits, 1983.
11. L.G. Heller, W.R. Griffin, J.W. Davis, and N.G. Thoma. Cascode voltage switch logic: A differential CMOS logic family. In IEEE International Solid State Circuits Conference, 1984.
12. V. Peng, D.R. Donchin, and Y.-T. Yen. Design methodology and CAD tools for the NVAX microprocessor. In IEEE Int. Conf. on Computer Design, 1992.
13. K. De, C. Wu, and P. Banerjee. Reliability driven logic synthesis of multilevel circuits. In International Symposium on Circuits and Systems, pages 1105-1108, 1992.
14. N.K. Jha and S.-J. Wang. Design and synthesis of self-checking VLSI circuits. IEEE Transactions on CAD, pages 878-887, 1993.
15. S.M. Reddy. Complete test sets for logic functions. IEEE Transactions on Computers, C-22:1016-1020, 1973.
16. F. Brglez, D. Bryan, and K. Kozminski. Combinational profiles for sequential benchmark circuits. In International Symposium on Circuits and Systems, pages 1929-1934, 1989.
17. S. Yang. Logic synthesis and optimization benchmarks user guide (version 3.0). Technical report, Microelectronics Center of North Carolina, P.O. Box 12889, Research Triangle Park, NC 27709, January 1991.
18. S.B. Akers. Universal test sets for logic networks. IEEE Transactions on Computers, C-22:835-839, 1973.
19. G. Gupta and N.K. Jha. A universal test set for CMOS circuits. IEEE Transactions on CAD, 7:590-597, 1988.
20. B. Chen and C.L. Lee. A complement-based fast algorithm to generate universal test sets for multi-output functions. IEEE Transactions on CAD, 13:370-377, 1994.
21. Z. Kohavi. Switching and Finite Automata Theory. McGraw-Hül, 1978.
22. W.K. Lam, A. Saldanha, R.K. Brayton, and A.L. Sangiovanni-Vincentelli. Delay fault coverage and performance tradeoffs. In 30th Design Automation Conference, pages 446-451, 1993.
23. E. Sentovich, K. Singh, C. Moon, H. Savoj, R. Brayton, and A. Sangiovanni-Vincentelli. Sequential circuit design using synthesis and optimization. In International Conference on Computer Design, pages 328-333, 1992.
24. A.K. Pramanick and S. Kundu. Design of scan-based path delay testable sequential circuits. In International Test Conference, pages 962-971, 1993.