Partially parallel scan chain for test length reduction by using retiming technique

Proceedings of the Asian Test Symposium

Volumn , Issue , 1996, Pages 94-99

  Higami, Yoshinobu ^a   Kajihara, Seiji ^a   Kinoshita, Kozo ^a  

^a OSAKA UNIVERSITY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

DESIGN FOR TESTABILITY; SCAN DESIGNED CIRCUITS; TEST VECTOR GENERATION;

ELECTRIC FAULT CURRENTS; FLIP FLOP CIRCUITS; INTEGRATED CIRCUIT TESTING; MATHEMATICAL TRANSFORMATIONS; SEQUENTIAL CIRCUITS; VECTORS;

LSI CIRCUITS;

EID: 0030419970     PISSN: 10817735     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (7)

1. C. E. Leiserson and J. B. Saxe, "Retiming Synchronous Circuitry," Algorithmica, vol. 6, pp. 5-35,1991.
2. S. Malik, E. M. Sentovich, R. K. Brayton and A. Sangiovanni-Vincentelli, "Retiming and Resynthesis: Optimizing Sequential Networks with Combinational Techniques", IEEE Trans, on Comput.-Aided Design, vol. 10, pp. 74-84, Jan. 1991.
3. De Micheli, "Synchronous Logic Synthesis: Algorithms for Cycle-Time Minimization", IEEE Trans, on Cómput.-Aided Design, vol. 10, pp. 63-73, Jan. 1991.
4. H. Yotsuyanagi, S. Kajihara and K. Kinoshita, "Synthesis for Testability by Sequential Redundancy Removal Using Retiming," Proc. Symp. Fault Tolerant Computing, pp. 33-40, June 1995.
5. A. El-Maleh, T. Marchok, J Rajski and W. Maly, "On Test Set Preservation of Retimed Circuits," Proc. Design Automation Conf., pp. 176-182, June 1995.
6. Y. Higami, S. Kajihara and K. Kinoshita, "Test Sequence Compaction by Reduced Scan Shift and Retiming," Proc. Asian Test Symp. pp. 169-175, Nov. 1995.
7. S. Kajihara, I. Pomeranz, K. Kinoshita and S. M. Reddy, "Cost-Effective Generation of Minimal Test Sets for Stuck-at Faults in Combinational Logic Circuits," Proc. Design Automation Conf., pp. 102-106, June 1993.