Defect-oriented vs schematic-level based fault simulation for mixed-signals ICs

IEEE International Test Conference (TC)

Volumn , Issue , 1996, Pages 511-520

  Olbrich, Thomas ^a   Perez, Jordi ^a   Grout, Ian A ^a   Richardson, Andrew M D ^a   Ferrer, Carles ^a  

^a LANCASTER UNIVERSITY   (United Kingdom)

Author keywords

[No Author keywords available]

Indexed keywords

COST EFFECTIVENESS; ELECTRIC FAULT CURRENTS; INTEGRATED CIRCUIT LAYOUT; MIXER CIRCUITS; OPTIMIZATION; PROBABILITY; SEMICONDUCTOR DEVICE MODELS;

INDUCTIVE FAULT ANALYSIS; MIXED SIGNAL INTEGRATED CIRCUITS; SWITCHED CURRENT DESIGN; TRANSISTOR FAULT MODEL;

INTEGRATED CIRCUIT TESTING;

EID: 0030419314     PISSN: 10893539     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (16)