Distributed binary decision diagrams for verification of large circuits

Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors

Volumn , Issue , 1996, Pages 365-370

  Arunachalam, Prakash ^a   Chase, Craig ^a   Moundanos, Dinos ^a  

^a INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BINARY SEQUENCES; COMPUTER WORKSTATIONS; DATA STORAGE EQUIPMENT; DECISION TABLES; EQUIVALENCE CLASSES; LOGIC DESIGN; SEQUENTIAL CIRCUITS; STORAGE ALLOCATION (COMPUTER);

BINARY DECISION DIAGRAMS (BDD);

INTEGRATED CIRCUIT TESTING;

EID: 0030416476     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (13)