Physically based description of quasi-saturation region of vertical DMOS power transistors

Technical Digest - International Electron Devices Meeting, IEDM

Volumn , Issue , 1996, Pages 489-492

  Kreuzer, C H ^a   Krischke, N ^a   Nance, P ^a  

^a BUNDESWEHR UNIVERSITY MUNICH   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

INTEGRATED CIRCUIT MANUFACTURE; TIMING CIRCUITS; COMPUTER SIMULATION; ELECTRIC CURRENTS; ELECTRIC RESISTANCE; ELECTRONS; GATES (TRANSISTOR); POWER ELECTRONICS; SEMICONDUCTOR DEVICE MODELS; SEMICONDUCTOR DOPING;

'CURRENT; CIRCUIT DESIGNS; CIRCUIT SIMULATORS; COMPACT MODEL; PHYSICALLY BASED; POWER; QUASI-SATURATION; SATURATION BEHAVIOR; SATURATION REGION; VERTICAL DMOS;

CIRCUIT SIMULATION; MOSFET DEVICES;

CIRCUIT SIMULATOR; ELECTRON INJECTION; QUASI SATURATION REGION; VERTICAL DMOS POWER TRANSISTORS;

EID: 0030416406     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IEDM.1996.553844     Document Type: Conference Paper

References (5)

1. [l] Yeong-Seuk Kim and Jerry G. Fossum. Physical DMOST modeling for high-voltage IC CAD. IEEE Transactions on Electron Devices, 37(3):797-803, 1990.
2. [Z]Jacinto Paredes, Salvador Hidalgo, Francisco Berta, Juan Fernandez, Jose Rebollo, and Jose Millan. A steady-state VDMOS transistor model. IEEE Transactions on Electron Devices, 39(3):712-719, 1992.
3. Martin Stiftinger. Simulation und Modellierung von HochvoltDMOS-Transistoren. PhD thesis, Technische Universitat Wien, August 1994.
4. S. C.Sun and James D. Plummer. Modeling of the on-resistance of LDMOS, VDMOS and VMOS power transistors. IEEE Transactions on Electron Devices, ED-27(2):356-367,Feb. 1980.
5. TMA. MEDICI Users Manual Version 2.2, June 1996.