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Volumn 14, Issue 3, 1996, Pages 265-282

Narrow-band FIR filtering with FPGAs using sigma-delta modulation encoding

Author keywords

[No Author keywords available]

Indexed keywords

DATA QUANTIZATION;

EID: 0030415643     PISSN: 09225773     EISSN: None     Source Type: Journal    
DOI: 10.1007/BF00929620     Document Type: Review
Times cited : (3)

References (13)
  • 1
    • 0006506250 scopus 로고
    • FPGA-implementable digital filters
    • W. Moore and W. Luk (Eds.), Abingdon EE&CS Books, Oxford, England
    • J. Isoaho, "FPGA-implementable digital filters," More FPGAs, W. Moore and W. Luk (Eds.), Abingdon EE&CS Books, Oxford, England, pp. 281-290, 1994.
    • (1994) More FPGAs , pp. 281-290
    • Isoaho, J.1
  • 2
    • 0029273997 scopus 로고
    • Automatic implementation of FIR filters on field programmable gate arrays
    • March
    • S. Mohanakrishnan and J.B. Evans, "Automatic implementation of FIR filters on field programmable gate arrays," IEEE Signal Processing Letters, Vol. 2, No. 3, pp. 51-53, March 1995.
    • (1995) IEEE Signal Processing Letters , vol.2 , Issue.3 , pp. 51-53
    • Mohanakrishnan, S.1    Evans, J.B.2
  • 5
    • 85033051406 scopus 로고
    • Trade-off between FPGA resource utilization and roundoff error in optimized CSD FIR digital filters
    • IEEE Computer Society Press, Pacific Grove, California, Oct. 31-Nov. 2
    • A.E. de la Serna and M.A. Soderstrand, "Trade-off between FPGA resource utilization and roundoff error in optimized CSD FIR digital filters," Twenty-Eighth Asilomar Conference on Signals, Systems & Computers, IEEE Computer Society Press, Pacific Grove, California, pp. 120-127, Oct. 31-Nov. 2, 1994.
    • (1994) Twenty-Eighth Asilomar Conference on Signals, Systems & Computers , pp. 120-127
    • De La Serna, A.E.1    Soderstrand, M.A.2
  • 6
    • 53349151138 scopus 로고
    • Implementing digital signal processing algorithms using pipelined bit-serial arithmetic and field programmable gate arrays
    • P.J. Graumann and L.E. Turner, "Implementing digital signal processing algorithms using pipelined bit-serial arithmetic and field programmable gate arrays," Proceedings of FPGA 1992, pp. 123-128, 1992.
    • (1992) Proceedings of FPGA 1992 , pp. 123-128
    • Graumann, P.J.1    Turner, L.E.2
  • 7
    • 0027640821 scopus 로고
    • FIR filters with field-programmable gate arrays
    • L. Mintzer, "FIR filters with field-programmable gate arrays," Journal of VLSI Signal Processing, No. 6, pp. 120-127, 1993.
    • (1993) Journal of VLSI Signal Processing , Issue.6 , pp. 120-127
    • Mintzer, L.1
  • 8
    • 0024700020 scopus 로고
    • Applications of distributed arithmetic to digital signal processing
    • July
    • S.A. White, "Applications of distributed arithmetic to digital signal processing," IEEE ASSP Magazine, Vol. 6, No. 3, pp. 4-19, July 1989.
    • (1989) IEEE ASSP Magazine , vol.6 , Issue.3 , pp. 4-19
    • White, S.A.1
  • 10
    • 0010863629 scopus 로고
    • 16-tap, 8-bit FIR filter applications guide
    • Nov.
    • G. Goslin and B. Newgard, "16-tap, 8-bit FIR filter applications guide," Xilinx Application Note, pp. 25-28, Nov. 1994.
    • (1994) Xilinx Application Note , pp. 25-28
    • Goslin, G.1    Newgard, B.2
  • 12
    • 0343524096 scopus 로고
    • 0401098 01, April
    • Xilinx Inc. XACT Libraries Guide, 0401098 01, April 1994.
    • (1994) XACT Libraries Guide
  • 13


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.