Optimization of custom MOS circuits by transistor sizing

IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers

Volumn , Issue , 1996, Pages 174-180

  Conn, Andrew R ^a   Coulman, Paula K ^a   Hating, Ruud A ^a   Morrill, Gregory L ^a   Visweswariah, Chandu ^a  

^a IBM T J WATSON RESEARCH CENTER   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; INTEGRATED CIRCUIT LAYOUT; MOS DEVICES; OPTIMIZATION; USER INTERFACES;

AUTOMATIC TRANSISTOR SIZING; SOFTWARE PACKAGE CADENCE; SOFTWARE PACKAGE JIFFYTUNE; SOFTWARE PACKAGE LANCELOT; SOFTWARE PACKAGE SLED;

APPLICATION SPECIFIC INTEGRATED CIRCUITS;

EID: 0030415443     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (34)