Selective self-aligned emitter ledge formation for heterojunction bipolar transistors

IEEE Electron Device Letters

Volumn 17, Issue 12, 1996, Pages 555-556

  Fresina, M T ^a,b   Hartmann, Q J ^a,b   Stillman, G E ^a,b  

^a UNIVERSITY OF ILLINOIS AT URBANA CHAMPAIGN   (United States)

^b IEEE

Author keywords

[No Author keywords available]

Indexed keywords

ETCHING; FABRICATION; PASSIVATION; SCANNING ELECTRON MICROSCOPY; SEMICONDUCTING GALLIUM ARSENIDE; SEMICONDUCTING INDIUM COMPOUNDS; SEMICONDUCTOR DEVICE MANUFACTURE; SEMICONDUCTOR DEVICE STRUCTURES;

LEDGE FABRICATION; SELF ALIGNED EMITTER PASSIVATION LEDGE; WET CHEMICAL ETCHING;

HETEROJUNCTION BIPOLAR TRANSISTORS;

EID: 0030414884     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/55.545768     Document Type: Article

References (8)

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