Analytical modeling for the collector current in SOI gate-controlled hybrid transistor

Solid-State Electronics

Volumn 39, Issue 12, 1996, Pages 1816-1818

  Huang, Ru ^a   Wang, Yang Yuan ^a   Han, RuQi ^a  

^a PEKING UNIVERSITY   (China)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTATIONAL METHODS; COMPUTER SIMULATION; DIFFUSION IN SOLIDS; ELECTRIC CURRENTS; GATES (TRANSISTOR); ITERATIVE METHODS; SEMICONDUCTOR DEVICE MODELS; SILICON ON INSULATOR TECHNOLOGY; SURFACE PROPERTIES;

COLLECTOR CURRENT; DRIFT COMPONENT; GATE CONTROLLED HYBRID TRANSISTORS (GCHTS); GUMMEL PLOTS; SURFACE POTENTIAL;

BIPOLAR TRANSISTORS;

EID: 0030414417     PISSN: 00381101     EISSN: None     Source Type: Journal    
DOI: 10.1016/S0038-1101(96)00118-9     Document Type: Article

References (8)

1. J. P. Colinge, IEEE Trans. Electron. Devices ED-34, 845 (1987).
2. S. A. Parke, C. Hu and P. K. Ko, IEEE Int. SOI Conf. 82 (1992).
3. S. Verdonckt-Vandebroek, S. S. Wong, J. C. S. Woo and P. K. Ko, IEEE Trans. Electron. Devices ED-38, 2487 (1991).
4. K. S. Seo and C. K. Kim, IEEE Trans. Electron. Devices ED-27, 295 (1980).
5. D. Seltz, I. Kidron, A two-dimensional model for the lateral p-n-p transistor, IEEE Trans. Electron. Devices ED-21, 587 (1974).
6. S. M. Sze, Physics of Semiconductor Devices. Wiley, New York (1981).
7. T. H. Huang and M. J. Chen, Solid-State Electron. 38, 115 (1995).
8. P. Chen, Z. J. Li and L. T. Liu, ICSICT'95, 787 (1995).