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Volumn 20, Issue 4, 1996, Pages 461-472

Systolic processor designs using single-electron digital circuits

Author keywords

Coulomb blockade; Error correction; Single electron digital circuits; Systolic processors

Indexed keywords

DIGITAL SIGNAL PROCESSING; ERROR CORRECTION; SYSTOLIC ARRAYS;

EID: 0030413356     PISSN: 07496036     EISSN: None     Source Type: Journal    
DOI: 10.1006/spmi.1996.0103     Document Type: Article
Times cited : (11)

References (39)
  • 2
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    • G. W. Anderson, D. C. Webb, A. E. Spezio and J. N. Lee, Proc. IEEE 79, 355 (1991). To meet the requirements of these specialized applications the present approach is to use analog and often non-electronic (e.g. acousto-optic) signal processing methods.
    • (1991) Proc. IEEE , vol.79 , pp. 355
    • Anderson, G.W.1    Webb, D.C.2    Spezio, A.E.3    Lee, J.N.4
  • 10
    • 22244475650 scopus 로고    scopus 로고
    • note
    • Locally-interconnected architectures are computationally-universal; the issue here is one of efficiency.
  • 12
    • 0002412043 scopus 로고
    • Edited by H. Grabert and M. Devoret, Plenum, New York, Ch. 9
    • D. V. Averin and K. K. Likharev, in Single Charge Tunneling, Edited by H. Grabert and M. Devoret, Plenum, New York, Ch. 9 (1992).
    • (1992) Single Charge Tunneling
    • Averin, D.V.1    Likharev, K.K.2
  • 16
    • 85027160086 scopus 로고
    • An electron-turnstile-based design for a single-electron switch has been given by K. Nakazato and J. D. White, IEDM Tech. Dig. p. 487 (1992).
    • (1992) IEDM Tech. Dig. , pp. 487
    • Nakazato, K.1    White, J.D.2
  • 26
    • 0030086743 scopus 로고    scopus 로고
    • A. S. Ashur, M. K. Ibrahim and A. Aggoun, IEE Proc.-E 143, 14 (1996). The intermediate approaches which allow the number of bits processed in parallel to be varied and optimized are termed digit-serial.
    • (1996) IEE Proc.-E , vol.143 , pp. 14
    • Ashur, A.S.1    Ibrahim, M.K.2    Aggoun, A.3
  • 29
    • 84966217500 scopus 로고
    • S. Winograd, Math. Comput. 32, 175 (1978), this reference provides algorithms for computing DFTs with 2, 3, 4, 5, 7, 9 and 16 points;
    • (1978) Math. Comput. , vol.32 , pp. 175
    • Winograd, S.1
  • 34
    • 0003133883 scopus 로고
    • Edited by C. E. Shannon and J. McCarthy, Princeton Univ. Press
    • J. v. Neumann, in Automata Studies, Edited by C. E. Shannon and J. McCarthy, Princeton Univ. Press, pp. 43-98 (1956).
    • (1956) Automata Studies , pp. 43-98
    • Neumann, J.V.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.