Hybrid pin control using boundary-scan and its applications

Proceedings of the Asian Test Symposium

Volumn , Issue , 1996, Pages 44-49

  Ke, Wuudiann ^a  

^a LUCENT TECHNOLOGIES   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BOUNDARY SCAN METHOD; MICROCHIP PINS;

CODES (STANDARDS); COMPUTER AIDED ANALYSIS; ELECTRIC CONNECTORS; ELECTRIC FAULT CURRENTS; LOGIC DESIGN; MICROPROCESSOR CHIPS;

INTEGRATED CIRCUIT TESTING;

EID: 0030412867     PISSN: 10817735     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)

1. Chau, Savio, "Fault Injection Boundary Scan Design for Verification of Fault Tolerant Systems", Proc. of International Test Conference, Oct. 1994, pp. 677-681.
2. IEEE Standard 1149.1-1990, IEEE Standard Test Access Port and Boundary-Scan Architecture, IEEE Computer Society.
3. Nadeau-Dostie, B. et. al., "A new hardware fault insertion scheme for system diagnostics verification", Proc. of International Test Conference, Oct. 1995, pp. 994-1002.
4. Parker, K. The Boundary-Scan Handbook, Kluwer Academic Publishers, 1992.
5. Sedmak, R.,"Boundary-Scan: Beyond Production Tests", Proc. of 12th VLSI Test Symposium, 1994, pp. 415-420.