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Volumn , Issue , 1996, Pages 179-182
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Effects of buried p-layers on substrate-trap induced phenomena in GaAs MESFETs
a a a
a
NEC CORPORATION
(Japan)
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Author keywords
[No Author keywords available]
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Indexed keywords
CAPACITANCE;
ELECTRIC RESISTANCE;
MATHEMATICAL MODELS;
SEMICONDUCTING GALLIUM ARSENIDE;
SEMICONDUCTOR DEVICE STRUCTURES;
SUBSTRATES;
SURFACE PHENOMENA;
TRANSIENTS;
BURIED P LAYERS;
FREQUENCY DISPERSION;
SELF-BACKGATING MODEL;
TRAP INDUCED PHENOMENA;
MESFET DEVICES;
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EID: 0030410854
PISSN: None
EISSN: None
Source Type: Conference Proceeding
DOI: None Document Type: Conference Paper |
Times cited : (4)
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References (4)
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