Global algorithm for the partial scan design problem using circuit state information

IEEE International Test Conference (TC)

Volumn , Issue , 1996, Pages 548-557

  Xiang, Dong ^a   Patel, Janak H ^a  

^a UNIVERSITY OF ILLINOIS AT URBANA CHAMPAIGN   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMPUTER AIDED LOGIC DESIGN; COMPUTER SIMULATION; FLIP FLOP CIRCUITS; LOGIC CIRCUITS; OPTIMIZATION;

CIRCUIT STATE INFORMATION; DYNAMIC TESTABILITY; GLOBAL PARTIAL SCAN DESIGN ALGORITHM;

INTEGRATED CIRCUIT TESTING;

EID: 0030409508     PISSN: 10893539     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (26)