A New Planar Stacked Technology(PST) for Scaled and Embedded DRAMs

Technical Digest - International Electron Devices Meeting, IEDM

Volumn , Issue , 1996, Pages 597-600

  Sim, S P ^a   Lee, W S ^a   Ohu, Y S ^a   Choe, H C ^a   Kim, J H ^a   Ban, H D ^a   Kim, I C ^a   Chang, Y H ^a   Lee, Y J ^a   Kang, H K ^a   Chung, U I ^a   Choi, C S ^a   Hwang, C G ^a  

^a SAMSUNG Electronics   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

BIT LINES; CAPACITOR DIELECTRICS; CAPACITOR FORMATION; EMBEDDED DRAM; KEY FEATURE; PLUG STRUCTURES; SCALINGS; SELF-ALIGNED; STACK TECHNOLOGY; TRENCH ISOLATION;

COMPUTER CIRCUITS; RANDOM ACCESS STORAGE;

CAPACITORS; DIELECTRIC MATERIALS; ELECTRIC PROPERTIES; LOGIC CIRCUITS; PHOTOLITHOGRAPHY; POLISHING; TANTALUM COMPOUNDS;

CHEMICAL MECHANICAL POLISHING; DYNAMIC RANDOM ACCESS STORAGE; METALLIZATION; PLANAR STACKED TECHNOLOGY; SELF ALIGNED POLY PLUG STRUCTURE; SHALLOW TRENCH ISOLATION;

EID: 0030409290     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IEDM.1996.554054     Document Type: Conference Paper

References (1)

1. [l] Y. Ohji et. al., Tech. Dig. OfIEDM, 1995,p l l l