Reliable logic circuits with byte error control codes - a feasibility study

IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems

Volumn , Issue , 1996, Pages 286-294

  Lo, Jien Chung ^a   Kitakami, Masato ^a   Fujiwara, Eiji ^a  

^a UNIVERSITY OF RHODE ISLAND   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CODING ERRORS; ERROR CORRECTION; INTEGRATED CIRCUIT MANUFACTURE; INTEGRATED CIRCUIT TESTING; MASKS; REDUNDANCY;

BYTE ERROR CONTROL CODES; TRIPLE MODULO REDUNDANCY (TMR);

LOGIC CIRCUITS;

EID: 0030407377     PISSN: 10636722     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (12)