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Volumn , Issue , 1996, Pages 265-275
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Methodology for layout design and optimization of ESD protection transistors
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Author keywords
[No Author keywords available]
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Indexed keywords
CMOS INTEGRATED CIRCUITS;
CORRELATION METHODS;
CURRENT VOLTAGE CHARACTERISTICS;
ELECTRIC DISCHARGES;
ELECTROSTATICS;
MATHEMATICAL MODELS;
OPTIMIZATION;
RANDOM ACCESS STORAGE;
ELECTROSTATIC DISCHARGE (ESD) PROTECTION TRANSISTORS;
HUMAN BODY MODEL (HBM);
STATIC RANDOM ACCESS MEMORY (SRAM);
TRANSMISSION LINE PULSING;
TRANSISTORS;
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EID: 0030406675
PISSN: 07395159
EISSN: None
Source Type: Conference Proceeding
DOI: None Document Type: Conference Paper |
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Times cited : (25)
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References (15)
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