Optimizing high-level synthesis for self-checking arithmetic circuits

IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems

Volumn , Issue , 1996, Pages 268-276

  Antola, A ^a   Piuri, V ^a   Sami, M G ^a  

^a POLITECNICO DI MILANO   (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMPUTER ARCHITECTURE; ELECTRIC NETWORK SYNTHESIS; ENCODING (SYMBOLS); ERROR DETECTION; INTEGRATED CIRCUIT TESTING; OPTIMIZATION;

DATA FLOW GRAPH; REGISTER LEVEL ARCHITECTURE; SELF CHECKING ARITHMETIC CIRCUITS;

VLSI CIRCUITS;

EID: 0030405343     PISSN: 10636722     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (10)