Performance-oriented circuit partitioning algorithm with logic-block replication for multi-FPGA systems

IEEE Asia-Pacific Conference on Circuits and Systems - Proceedings

Volumn , Issue , 1996, Pages 294-297

  Togawa, Nozomu ^a   Sato, Masao ^a   Ohtsuki, Tatsuo ^a  

^a WASEDA UNIVERSITY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; CONSTRAINT THEORY; CRITICAL PATH ANALYSIS; ERROR DETECTION; ERRORS; LOGIC GATES; OPTIMIZATION;

CIRCUIT PARTITIONING ALGORITHM; CRITICAL SIGNAL PATH; FIELD PROGRAMMABLE GATE ARRAYS; LOGIC BLOCK REPLICATION; NETWORK FLOW TECHNIQUE; PATH DELAY CONSTRAINT; UPPER BOUND;

LOGIC DESIGN;

EID: 0030403082     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (14)